Mws5101, mws5101a

MWS5101,
MWS5101A
256-Word x 4-Bit
LSI Static RAM
Features
Description
• Industry Standard Pinout
The MWS5101 and MWS5101A are 256 word by 4-bit staticrandom access memories designed for use in memory • Very Low Operating Current . . . . . . . . . . . . . . . . . . 8mA
systems where high speed, very low operating current, and at VDD = 5V and Cycle Time = 1µs
simplicity in use are desirable. They have separate data • Two Chip Select Inputs Simple Memory Expansion
inputs and outputs and utilize a single power supply of 4V to6.5V. The MWS5101 and MWS5101A differ in input voltage • Memory Retention for Standby. . . . . . . . . . . . . 2V (Min)
characteristics (MWS5101A is TTL compatible).
Battery Voltage
Two Chip Select inputs are provided to simplify system • Output Disable for Common I/O Systems
expansion. An Output Disable control provides Wire-OR • Three-State Data Output for Bus Oriented Systems
capability and is also useful in common Input/Outputsystems by forcing the output into a high impedance state • Separate Data Inputs and Outputs
during a write operation independent of the Chip Select input • TTL Compatible (MWS5101A)
condition. The output assumes a high impedance statewhen the Output Disable is at high level or when the chip isdeselected by CS1 and/or CS2.
The high noise immunity of the CMOS technology ispreserved in this design. For TTL interfacing at 5V operation, MWS5101, MWS5101A
excellent system noise margin is preserved by using an (PDIP, SBDIP)
external pull-up resistor at each input.
For applications requiring wider temperature and operatingvoltage ranges, the mechanically and functionally equivalent The MWS5101 and MWS5101A types are supplied in 22 lead hermetic dual-in-line, sidebrazed ceramic packages (D suffix), in 22 lead dual-in-line plastic packages (E suffix), and Ordering Information
MWS5101A
TEMP. RANGE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright Intersil Corporation 19996-56 MWS5101, MWS5101A
OPERATIONAL MODES
CHIP SELECT 1
CHIP SELECT 2
READ/WRITE
DISABLE (OD)
NOTE: Logic 1 = High, Logic 0 = Low, X = Don’t Care.
Functional Block Diagram
† † †
DECODERS
DESELECT
FUNCTION
12 ††
14 ††
DECODERS
DECODERS
DECODERS
DECODERS
ALL COLUMNS
DESELECT
FUNCTION
† † †
† INPUT PROTECTION
† † OUTPUT
† † † OVER VOLTAGE
PROTECTION
PROTECTION
MWS5101, MWS5101A
Absolute Maximum Ratings
Thermal Information
(All Voltages Referenced to VSS Terminal) . . . . . . . . -0.5V to +7V PDIP Package . . . . . . . . . . . . . . . . . . .
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V SBDIP Package . . . . . . . . . . . . . . . . . .
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oCPackage Type E . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC Maximum Storage Temperature Range (TSTG) . . .-65oC to +150oCMaximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oCPlastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Maximum Lead Temperature (During Soldering) At distance 1/16 ±1/32 In. (1.59 ±0.79mm)from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC Recommended Operating Conditions
At TA = Full Package Temperature Range. For maximum reliability, operating conditionsshould be selected so that operation is always within the following ranges: PARAMETER
Static Electrical Specifications
CONDITIONS
MWS5101A
PARAMETER
1. Typical values are for TA = +25oC and nominal VDD.
2. Outputs open circuited; Cycle time = 1µs.
MWS5101, MWS5101A
Dynamic Electrical Specifications at TA = 0oC to +70oC, VDD = 5V ±5%
LIMITS (NOTE 1)
PARAMETER
1. MWS5101: tR, tF = 20ns, VIH = 0.7VDD, VIL = 0.3VDD; CL = 100pF and MWS5101A: tR, tF = 20ns, VIH = 2.2V, VIL = 0.65V; CL = 50pF 2. Time required by a limit device to allow for the indicated function.
3. Typical values are for TA = 25oC and nominal VDD.
MWS5101, MWS5101A
CHIP SELECT 1
CHIP SELECT 2
OUTPUT DISABLE
READ/WRITE
IMPEDANCE
IMPEDANCE
FIGURE 1. READ CYCLE TIMING WAVEFORMS
CHIP SELECT 1
CHIP SELECT 2
OUTPUT DISABLE
DATA IN STABLE
READ/WRITE
DON’T CARE
NOTE: tODS is required for common I/O operation only; for separate I/O operations, output disable is “don’t care”.
FIGURE 2. WRITE CYCLE TIME WAVEFORMS
MWS5101, MWS5101A
Data Retention Specifications at TA = 0oC to +70oC; See Figure 3
CONDITIONS
ALL TYPES
PARAMETER
1. Typical Values are for TA = 25oC and nominal VDD.
DATA RETENTION
FIGURE 3. LOW VDD DATA RETENTION TIMING WAVEFORMS
FIGURE 4. MEMORY CELL CONFIGURATION
MWS5101, MWS5101A
CONTROL A
A
CHIP-SELECT
CONTROL
CONTROL B
CHIP-SELECT AND
R/W CONTROL
CONTROL C
FIGURE 5. LOGIC DIAGRAM OF CONTROLS FOR MWS5101, MWS5101A
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time withoutnotice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurateand reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties whichmay result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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